rev. 0.1 8/15 copyright ? 2015 by silicon laborato ries SI8920ISO-EVB SI8920ISO-EVB SI8920ISO-EVB u ser ? s g uide description this document describes the operation of the SI8920ISO-EVB. kit contents ? the si8920iso evaluation kit contains the following items: ? SI8920ISO-EVB. ? si8920bc-ip installed on the evaluation board. SI8920ISO-EVB overview
SI8920ISO-EVB 2 rev. 0.1 1. hardware overview and setup 1.1. connecting to the evb power the evb by applying isolated 3.0 to 5.5 v dc supplies to terminal blocks j1 and j2. leds d21 and d22 will light up. use separate test points tp1, tp2, tp3, and tp4 for observing vdda, gnda, vddb, and gndb, respectively. note: do not place jumpers across jp10, jp11, or jp12. these are redundant test points for vdda, vddb, and aop/aon, respectively. there are three connection points for applying and obse rving differential signals to the inputs of si8920: 1. through a two conductor ribbon cable to 2x1 header jp8. 2. clipping wires to test points tp7 and tp8. 3. soldering wires directly to through holes located at tp9 and tp10. the same connector options are available for observin g and taking the output signals off circuit board: 1. through a two conductor ribbon cable at 2x1 header jp12. 2. clipping wires to test points tp5 and tp6. 3. soldering wires directly through holes located at tp11 and tp12. 1.2. driving si8920 inputs drive the inputs with a low impedance source. the si8920 has a typical input impedance of 37.2 k ? . a high source impedance will affect the gain error of the amplifier. the maximum specified differential voltage is 200 mv and the common mode must be within ?250 mv to 1 v with respect to gnda. note: when driving inputs from a single-ended source, short the unused input to gnda. if driving aip input, install 0 ? resistor across c23 pads. if driving ain input, install a 0 ? resistor across c24 pads.
SI8920ISO-EVB rev. 0.1 3 1.3. input configuration to measure input offset, install a jumper (not provided ) at jp8 to short aip and ai n together, and measure the difference voltage between aop and aon. si8920 has a channel bandwidth of approximately 750 khz. r9-c7-r10 are populated providing low pass filtering with cutoff frequency of approximately 400 khz. if a different cutoff frequency is desired, replace c7 per table 1. if it is necessary to replace r9 and r10 for a specific cutoff frequency, ensure that r9 = r10 < 33 ? . si8920 has excellent immunity to co mmon mode transients. this evb provides provisions for capacitors c23 and c24 (not populated) between each input pin and gnda. pl acing a small capacitor at c23 and c24 can assist with charge swapping between the inputs and gnda duri ng common mode transients. however, any mismatch between c23 and c24 will result as a gain er ror at th e output. 1.4. observing si8920 outputs use a differential probe when observing the output us ing an oscilloscope. most diff erential oscilloscope probes will connect to the 2x1 headers jp12 withou t adapters. if only single- ended oscilloscope probes are available, use two and set oscilloscope to subtract t he two channels as one channel will only show half of the output. table 1. input filter cutoff frequency for common capacitor values with r9 = r10 = 20 ? c7 (nf) cutoff frequency (khz) 10* 398 15 265 22 181 33 121 47 85 *note: installed value.
SI8920ISO-EVB 4 rev. 0.1 1.5. output configuration by default, r23 and r24 are populated with 0 ? resistors that pass the output si gnal to the output connectors. if low pass filtering at the output is requ ired, replace r23 and r24 and populate c22. r25 can be populated to measure the differential output drive strength. r26 and r27 can be populated to measure the common mode driv e strength to gndb. table 2. test point descriptions test point description reference tp1 vdda gnda tp2 gnda n/a tp3 vddb gndb tp4 gndb n/a tp5 aop gndb tp6 aon gndb tp7 aip gnda tp8 ain gnda tp13 gnda n/a tp14 gndb n/a table 3. jumper descriptions jumper pin 1 pin 2 default position description jp8 ain aip not installed analog input connector, short to measure offset jp10 vdda gnda not installed do not short ? test points only jp11 vddb gndb not installed do not short ? test points only jp12 aon aop not installed do not short ? test points only
SI8920ISO-EVB rev. 0.1 5 2. SI8920ISO-EVB schematics vdda tp2 gnda tp1 vdda vdda tp4 gndb tp3 vddb vddb jp8 jp10 jp11 output side power supply valid range: 3.3v to 5v +/ - 10% tp5 ao p tp6 ao n input connectors tp7 aip tp8 ai n tp9 ni tp10 ni tp11 ni tp12 ni jp12 output connectors do no t short do no t short do no t short d21 red input side power supply j1 1 2 valid ran ge: 3.3v to 5v +/ - 10% r22 10k d22 red j2 1 2 r21 10k d20 5.6v tp13 gnda tp14 gndb vddb h1 si8920 vdda gnda gndb vddb ai p ao n ao p ai n d23 5.6v figure 1. SI8920ISO-EVB schematic (1 of 2)
SI8920ISO-EVB 6 rev. 0.1 u 1 v d d a 1 a i p 2 a i n 3 g n d a 4 g n d b 5 a o n 6 a o p 7 v d d b 8 r 2 3 0 r 2 4 0 r 2 5 n i c 2 2 n i c 2 3 n i c 2 4 n i l o w p a s s f i l t e r c u t o f f a t 4 0 0 k h z o p t i o n a l o u t p u t f i l t e r r 2 6 n i r 2 7 n i v d d a g n d a c 5 0 . 1 u f c 4 1 0 u f r 9 2 0 . 0 r 1 0 2 0 . 0 c 7 0 . 0 1 u f c 1 2 0 . 1 u f c 1 0 1 0 u f g n d b v d d b a i p a o n a o p a i n figure 2. SI8920ISO-EVB schematic (2 of 2)
SI8920ISO-EVB rev. 0.1 7 3. SI8920ISO-EVB layout figure 3. SI8920ISO-EVB layout top bottom top silkscreen bottom silkscreen
SI8920ISO-EVB 8 rev. 0.1 4. bill of materials table 4. SI8920ISO-EVB bill of materials part reference description manufacturer manufacturer part number c4, c10 cap, 10 f, 10 v, 20%, x7r, 1206 venkel c1206x7r100-106m c5, c12 cap, 0.1 f, 10 v, 10%, x7r, 0603 venkel c0603x7r100-104k c7 cap, 0.01 f, 16 v, 10%, x7r, 0603 venkel c0603x7r160-103k d20, d23 dio, zener, 28 v, 500 mw, sod123 on semi mmsz5255bt1g d21, d22 led, red, 631 nm, 20 ma, 2 v, 54mcd, 0603 lite-on ltst-c190krkt j1, j2 conn, term block 2pos, 5mm pcb phoenix contact 1729018 jp8, jp10, jp11, jp12 header, 2x1, 0.1" pitch, ti n plated samtec tsw-102-07-t-s mh1, mh2, mh3, mh4 hdw, screw, 4-40 x 1/4" pan head, slotted, nylon richco plastic co nss-4-4-01 r9, r10 res, 20.0 ? , 1/10 w, 1%, thickfilm, 0603 venkel cr0603-10w-20r0f r21, r22 res, 10 k, 1/10 w, 5%, thickfilm, 0603 venkel cr0603-10w-103j r23, r24 res, 0 ? , 1a, thickfilm, 0603 venkel cr0603-16w-000 so1, so2, so3, so4 hdw, standoff, 1/4" hex, 4- 40x3/4", nylon keystone 1902d tp1, tp2, tp3, tp4, tp5, tp6, tp7, tp8 testpoint, black, pth kobiconn 151-203-rc u1 ic, isolated amplifier for current shunt measurement, 8pin smd gull wing silicon labs si8920bc-ip
SI8920ISO-EVB rev. 0.1 9 5. ordering guide table 5. SI8920ISO-EVB ordering guide ordering part number (opn) description si8920iso-kit si8920 analog is olator evaluation board kit
SI8920ISO-EVB 10 rev. 0.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.siliconlabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our cust omers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal soluti ons. silicon labs' extensive pat ent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibili ty for errors and omissions, and disclaim s responsibility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding t he suitability of its products for any par ticular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, in cluding without limitation consequential or incidental damages . silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmle ss against all claims and damages.
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